#rc -gui –f macro.tcl

set_attribute library [list osu018_stdcells.db]
set_attribute information_level 6
set myFiles [list toto.v] ;

set basename counter;
set runname RTL ;

set myClk clk;
set myPeriod_ps 10000 ;
set myInDelay_ps 250 ;
set myOutDelay_ps 250 ;

read_hdl toto.v
elaborate ${basename}


set clock [define_clock -period ${myPeriod_ps} -name ${myClk} [clock_ports]]
external_delay -input $myInDelay_ps -clock ${myClk} [find / -port ports_in/*]
external_delay -output $myOutDelay_ps -clock ${myClk} [find / -port ports_out/*]


check_design -unresolved
report timing -lint


synthesize -to_mapped


# Write out the reports
report timing > ${basename}_${runname}_timing.rep
report gates > ${basename}_${runname}_cell.rep
report power > ${basename}_${runname}_power.rep

write_hdl -mapped > ${basename}_${runname}.v
write_sdc > ${basename}_${runname}.sdc
