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# Generated by: | Cadence Encounter 13.10-p003_1
# OS: | Linux i686(Host ID patrice)
# Generated on: | Thu Jun 15 22:29:52 2017
# Design: /TD> | accu
# Command: | checkDesign -io -netlist -physicalLibrary -powerGround -tieHilo -timingLibrary -spef -floorplan -place -outdir checkDesign

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### Check Design Report

Design Stats

Design Name | accu
Number of cells used in the design | 9

Physical Library(LEF) Integrity Check

Cells with missing LEF | 0
Cells with missing PG PIN | 0
Cells with missing dimension | 0
Cells dimensions not multiple integer of site | 0
Cells pin with missing direction | 0
Cells pin with missing geometry | 0
Cells PG Pins with missing geometry | 0

Timing information check

Cells with missing Timing data | 9

SPEF Coverage

Annotation to Verilog Netlist | 0%
Annotation to Physical Netlist | 0%

Top Level Netlist Check

Floating Ports | 0
Ports Connect to multiple Pads | 0
Ports connected to core instances | 18

Instance Pin Check

Output pins connected to Power Ground net | 0
Instances with input pins tied together | 0
TieHi/Lo term nets not connected to instance's PG terms | 0
Floating Instance terminals | 0
Floating IO terms | 0
Tie Hi/Lo output terms floating | 0
Output term shorted to Power Ground net | 0

Primitive Net DRC Check

Nets with tri-state driver | 0
Nets with parallel drivers | 0
Nets with multiple drivers | 0
Nets with no driver (No FanIn) | 0
Output Floating nets (No FanOut) | 0
High Fanout nets (>50) | 0

Sub Module Port Definition Check

Tie Hi/Lo instances connected to output | 0
Verilog nets with multiple drivers | 0

Dont Use Cells Used in Design

Dont use cells in design | 0

I/O Pin Check

Unplaced I/O Pins | 0
Floating I/O Pins | 0
I/O Pins connected to Non-IO Insts | 18

Unplaced IO Pads

Unplaced I/O Pads | 0

Power Ground Nets

gnd | Routed
vdd | Routed

Power/Ground Pin Connectivity

Floating Power Ground terms | 0
Power/Ground pins connected to non Power/Ground net | 0
Power pin connected to Ground net | 0
Ground pin connected to Power net | 0

Top level Floorplan Check

Off-Grid Horizontal Tracks | 0
Off-Grid Vertical Tracks | 0
Placement grid on Mfg. grid | FALSE
User grid a multiple of Mfg. grid | FALSE
User grid a multiple of Mfg. grid | FALSE
Core Row grid not a multiple of Mfg. grid | 0
Horizontal GCell Grid off Mfg. grid | 0
Vertical GCell Grid off Mfg. grid | 0
AreaIO rows not on core-grid | 0
BlackBoxes Off Mfg. Grid | 0
Blocks Off Mfg. Grid | 0
BlackBoxes Off placement Grid | 0
Blocks off placement Grid | 0
Instances not snapped to row site | 0
Instances not on Mfg. Grid | 0
PrePlaced hard-macro pins not on routing grid | 0
Floating/Unconnected IO Pins | 0
Unplaced Io Pins | 0
IO Pin off Mfg. grid | 0
Overlapping IO pins | 0
Modules with off-grid Constraints | 0
Groups with off-grid Constraints | 0
Floating/Unconnected Ptn Pins | 0
Partition Pin off M. Grid | 0
Unplaced Partition Pins | 0
Partition Pin outside Partition box | 0
Overlapping Partition Pins | 0
Partition Pin Off-Track | 0
PartitionPower Domain off Grid | 0
PreRoute not on Mfg. grid | 0
Off Track Pre-Routes | 0
Off Grid Power/Ground Pre-routes | 0